Benutzer:00000: Unterschied zwischen den Versionen
Zeile 8: | Zeile 8: | ||
=== Course works === | === Course works === | ||
1. Electronic | 1. Electronic <br> | ||
2. Mathematics | |||
3. Computer Science | 2. Mathematics <br> | ||
4. Interactive system design | |||
5. Microcontroller | 3. Computer Science <br> | ||
6. Prototyping | |||
7. Control system | 4. Interactive system design <br> | ||
8. Embedded system | |||
9. Real Time system | 5. Microcontroller <br> | ||
10. Hardware software co-design | |||
11. Advanced embedded | 6. Prototyping <br> | ||
7. Control system <br> | |||
8. Embedded system <br> | |||
9. Real Time system <br> | |||
10. Hardware software co-design <br> | |||
11. Advanced embedded <br> | |||
12. Business communication | 12. Business communication | ||
Version vom 4. Juli 2023, 12:43 Uhr
Syed Rafsan Ishtiaque
Electronic Engineering
Hochschule Hamm-lippstadt
Contact: syed-rafsan.ishtiaque@stud.hshl.de
Course works
1. Electronic
2. Mathematics
3. Computer Science
4. Interactive system design
5. Microcontroller
6. Prototyping
7. Control system
8. Embedded system
9. Real Time system
10. Hardware software co-design
11. Advanced embedded
12. Business communication
Project works
1. Battleship & TicTacToe games based on C
→ Overall modelling of the system, Documentation, partial coding
2. Microcontroller: Autonomus car project
→ System modelling, Hardware installation, Arduino, Sensors
3. Prototyping: Amphibious rescue robot
→ Architecture designing, Sensors
4. Embedded electronic: Smart traffic light system
→ UML design, UPPAAL simulation, VHDL design
5. Advanced embedded: Smart green house modelling
→ System designing, configuration & modelling, Sensors and actuators, Documentation
6. Hardware engineering: Smart traffic light system (from hardware centric)
→ PCB designing, FPGA implementation, Project management
Paper writing
1. Real time system: Paper on "Priority Exchange" with process designing, server algorithm and UPPAAL modelling
2. Hardware software co-design: Paper on "Extended sequencing models in High level synthesis"